The Peripheral Component Interconnect Express (PCI-E) interface may be found in servers, desktops, and mobile PCs. An important power saving feature of PCI-E is Active State Power Management (ASPM). When L1 ASPM is enabled on a given PCI-E link, and the link has been inactive for a period of time (e.g. tens or hundreds of microseconds), the PCI-E link will transition to a L1 state that consumes much less power than the full power, fully functional L0 (on) state. While in the L1 state, the PCI-E clock may be stopped and a PLL may be powered down to save power. However, in order for a given device to start a DMA and transfer data across the PCI-E link, the link must be returned to the L0 state.
The process of transitioning from L1 to L0 is not instantaneous. This period of time is called the “L1 exit latency”. The L1 exit latency starts from the point in time a device determines that it needs to make a PCI-E transaction (e.g. a DMA) and initiates the transition to L0. The L1 exit latency ends when the PCI-E link has been fully transitioned to a L0 state. The precise L1 exit latency will depend on the design of the devices at both ends of the PCI-E link, but this may be greater than 20 microseconds if the PLL was not powered down and may be greater than 100 microseconds if the PLL was powered down.
Gigabit and Fast Ethernet Controllers may use a PCI-E bus to interface to the PC since PCI-E is a common high-speed peripheral interface. In addition, it is highly desirable for these Ethernet controllers with a PCI-E interface to support L1 ASPM so that the PCI-E link can automatically be put into a low power state during periods of inactivity on the interface. However, the long L1 latencies may negatively affect network responsiveness and performance. This is because the L1 exit latency can affect the latency that it takes for one network station to process and respond to a network packet that was sent by another network station. At Gigabit Ethernet speeds, even the addition of 10 microseconds of latency may be undesirable in some scenarios involving latency sensitive applications or benchmarks.
The L1 exit latency of a device depends on the physical layer design for that device. Trade-offs can be made between performance, cost, and complexity with the physical layer design. So the range of L1 exit latencies may very greatly from a bit less than 10 microseconds to hundreds of microseconds. Even devices with “lower” L1 exit latency may have exit latency greater than 30 (and sometimes greater than 100) microseconds from L1 when the PCI-E reference clock and PLL have been powered down, since the clock has to be restarted and the PLL has to re-acquire lock when transitioning to L0.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.